1. Field of the Invention
The present invention relates to a semiconductor integrated circuit equipped with an internal clock generating circuit which generates an internal clock, and a flip-flop circuit in which a plurality of latch circuits are cascaded via switch circuits which perform switching operations in synchronism with the internal clock.
An example of semiconductor integrated circuits as described above is a SDRAM (Synchronous Dynamic Random Access Memory).
2. Description of the Related Art
FIG. 1 is a block diagram of a conventional SDRAM. The SDRAM includes DRAM cores 1-1 and 1-2, a clock buffer 2, and a command decoder 3. The clock buffer 2 is used to receive an external clock CLK and a clock enable signal CKE. The command decoder 3 decodes a command defined by, for example, a chip select signal /CS, a row address strobe signal /RAS, a column address strobe signal /CAS and a write enable signal /WE.
The SDRAM includes an address buffer 4, and an I/O buffer 5. The address buffer is used to receive row and column address signals A0-A10 and a bank address signal A11. The I/O data buffer 5 is used to input and output I/O data DQ0-DQ3. A symbol DQM is an I/O data mask signal for masking I/O data.
The SDRAM includes control signal latch circuits 6-1 and 6-2, a mode register 7, and column address counters 8-1 and 8-2. The mode register 7 is used to make the setting of a CAS latency and a burst length. The column address counters 8-1 and 8-2 output column addresses depending on the burst length.
FIG. 2 is a block diagram specifically illustrating the clock buffer 2, the command decoder 3 and the control signal latch circuit 6-1 shown in FIG. 1. The clock buffer 2 includes an input buffer 10 for inputting the external clock CLK, and an input buffer 11 for inputting the clock enable signal CKE. The input buffer 10 is controlled so that the external clock CLK is input only when the clock enable signal CKE is at a high level.
The control signal latch circuit 6-1 includes an internal clock generating circuit 12 and a flip-flop circuit 13. The internal clock generating circuit 12 generates an internal clock Int-CLK synchronized with an incoming external clock CLK1 during a period in which the internal clock is needed. The flip-flop circuit 13 is used to latch an internal signal in synchronism with the internal clock Int-CLK and transfer the latched internal signal to the DRAM core 1-1. The flip-flop 13 is initialized by a power-on reset signal POR, which is set to the high level at the time of power on.
FIG. 3 is a circuit diagram of the flip-flop circuit 13, which is made up of four latch circuits 15, 18, 21, and 24. The latch circuit 15 is made up of a NOR circuit 16 and an inverter 17. The latch circuit 18 is made up of a NAND circuit 19 and an inverter 20. The latch circuit 21 is made up of a NOR circuit 22 and an inverter 23. The latch circuit 24 is made up of a NAND circuit 25 and an inverter 26.
The flip-flop circuit 13 also includes switch circuits 27, 30, 33 and 36. The switch circuit 27 is made up of a p-channel MOS (pMOS) transistor 28 and an n-channel (nMOS) transistor 29. The switch circuit 30 is made up of an nMOS transistor 31 and a pMOS transistor 32. The switch circuit 33 is made up of a pMOS transistor 34 and an nMOS transistor 35. The switch circuit 36 is made up of an nMOS transistor 37 and a pMOS transistor 38.
Further, the flip-flop circuit 13 includes inverters 39, 40 and 41. The inverter 39 inverts the power-on reset signal POR. The inverter 40 inverts the internal clock signal Int-CLK and thus controls on/off of the nMOS transistor 29 and 35 and the pMOS transistors 32 and 38. The inverter 41 inverts the output signal of the inverter 40 and thus controls on/off of the pMOS transistors 28 and 34 and the nMOS transistors 31 and 37.
In the SDRAM thus constructed, when a power supply voltage VCC rises at the time of power on, the power-on reset signal POR switches to the high level. Thus, in the flip-flop circuit 13, the output signals of the NOR circuits 16 and 22 are switched to the low level, and the output signals of the inverters 17 and 23 are switched to the high level. Thus, the latch circuits 15 and 21 are initialized, and nodes N1 and N3 are fixed to the low level, as shown in FIG. 4.
Further, the output signal of the inverter 39 is switched to the low level, and the output signals of the NAND circuits 19 and 25 are switched to the high level. Furthermore, the output signals of the inverters 20 and 26 are switched to the low level. Thus, the latch circuits 18 and 24 are initialized, and nodes N2 and N4 are fixed to the high level, as shown in FIG. 4.
That is, in the conventional SDRAM shown in FIG. 1, the internal clock Int-CLK is fixed to the low level or the high level until the internal clock Int-CLK is needed after the power supply voltage VCC rises at the time of power on in order to reduce power consumption. In the above case, if the levels of the nodes N1-N4 in the flip-flop circuit 13 are not fixed, the flip-flop circuit 13 will operate unstably and thus erroneous data may be output. In order to prevent occurrence of such erroneous data, the levels of the nodes N1-N4 are defined by the power-on reset signal POR.
However, the use of the power-on reset signal POR for defining the potential levels of the nodes N1-N4 needs the NOR circuits 16 and 22 for configuring the latch circuits 15 and 21 and the NAND circuits 19 and 25 for configuring the latch circuits 18 and 24. This increases the chip area and power consumption.